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14–4
Table 14–3 lists the parameters for the Clock_Derived block:
Table 14–3. Clock_Derived Block Parameters
Chapter 14: AltLab Library
Name
Base Clock Multiplicand
Numerator
Base Clock Multiplicand
Denominator
Reset Name
Reset Type
Export As Output Pin
Value
>= 1
>= 1
User defined
Active Low,
Active High,
Synchronized
Active Low,
Synchronized
Active High
On or Off
Description
Multiply the base clock period by this value. The resulting clock period should
be greater than 1ps but less than 2.1ms.
Divide the base clock period by this value. The resulting clock period should be
greater than 1ps but less than 2.1ms.
Specify a unique reset name. The default reset is aclr .
Specify whether the reset signal is active high or active low.
Turn on to export this clock as an output pin.
Display Pipeline Depth
The Display Pipeline Depth block controls whether the pipeline depth displays on
primitive blocks.
You can change the display mode by double-clicking on the block. When set, the
current pipeline depth displays at the top right corner of each block that adds latency
to your design. The currently selected mode shows on the Display Pipeline Depth
block symbol.
Changing modes causes a Simulink display update, which may be slow for very large
designs.
The Display Pipeline Depth block has no parameters.
HDL Entity
Use the HDL Entity block for black-box simulation subsystems that you include in
your design with a Subsystem Builder block. The HDL Entity block specifies the name
of the HDL file that DSP Builder substitutes for the subsystem and the names of the
clock and reset ports for the subsystem.
The Subsystem Builder block usually creates this block.
Table 14–4 shows the parameters for the HDL Entity block.
Table 14–4. HDL Entity Block Parameters
Name
HDL File Name
Value
User defined
Description
Specifies the name of the HDL file that DSP Builder substitutes for the subsystem
represented by a Subsystem Builder block.
Clock Name
Reset Name
User defined Specifies the name of the clock signal that the black-box subsystem uses.
User defined Specifies the name of the reset signal that the black-box subsystem uses.
HDL takes port names
from Subsystem
DSP Builder Handbook
On or Off
Turn on to use the subsystem port names as the entity port names instead of the
names of the HDL Input and HDL Output blocks.
November 2013 Altera Corporation
Volume 2: DSP Builder Standard Blockset
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